Layout of the chip (partial view)
Since different types of optical quality metrics are used to measure optical quality used for feedback in adaptive systems; however, usually, different types of imagers are needed to measure different metrics. Our chip has a high density (128 x 128 pixel) array that computes two optical metrics -- beam quality and image quality -- while also outputting the image incident on the array.
To optimize performance, the pixel used needs to be as small as possible, which is achieved by using a passive pixel consisting of two NMOS transistors with the source of one left floating, creating a photogate, while the other NMOS acts as a capacitor to store the charge generated by the incident light. Currently the pixel pitch is 26 x 15 lambda, allowing for an array of 130 x 130 pixels with a fill factor of 20%; however, the outermost ring is completely covered by Metal3, so it acts only as a dummy ring which reduces mismatch effects. Also, Metal3 covers the remainder of the array except for the photogates. The pixel design also further reduces the space needed since it inherently performs CDS, eliminating the need for more periphery computations. Above the array is a row of 128 shift registers each only 15 lambda wide, which results in perfect abutment between the registers and the appropriate pixels in the array to allow for selectign the columns of the pixel array that will generate output -- note that three columns must output for image quality computation, while only one column needs selected for beam quality and imaging computations. Beam quality computations are performed first, since calculating beam quality requires measuring the area of incident light by providing a measure of intensity squared, this is achieved by feeding the array output into an NMOS transistor which that creates a current proportional to the input voltage from the array, with respect to a reference voltage. The resulting currents from each of the array rows are placed onto a common wire, summing the currents to provide the final measure of beam quality. After calculating beam quality, image quality computations are performed, by calculating the number of edges, or transitions between light and dark, in the image. Image quality computation is done through the use of a spatial Laplacian kernel of the form , which is broken into two kernels and for ease of computation. The kernel computations are implemented by first storing three array row outputs on a sample-and-hold circuits, then the sum of each row is computed by a summing amplifier, and the three row sums are added together. After calculating these sums, the appropriate center pixel is chosen and the necessary difference is taken according to the kernel via a subtracting amplifier. Finally, a voltage rectifier is used to obtain the absolute value of obtained value. The basic functionality of the imaqe quality computation is described in the following block diagram:
Image Quality Computation
1 |
A.D. Bit1 -- One input to Address Decoder |
40 |
A.D. Bit2 -- Second input to Address Decoder |
2 |
SWCphi2A' -- Complement of SWCphi2A |
39 |
A.D. Bit3 -- Third input to Address Decoder |
3 |
SWCphi2A -- Other Switch Capacitor Clock |
38 |
A.D. Bit4 -- Fourth
input to Address Decoder |
4 |
SWCphi2' -- Complement of SWCphi1 |
37 |
A.D. Bit5 -- Fifth input to Address Decoder |
5 |
GND |
36 |
A.D. Bit6
-- Sixth input to Address Decoder |
6 |
SWCphi2 -- Switch
Capacitor Clock2 |
35 |
A.D. Bit7 --
Seventh input to Address Decoder |
7 |
SWCphi1'
--Complement of Switch Capacitor Clock 1 |
34 |
A.D. Output --
Address Decoder Output |
8 |
SWCphi1 -- Switch
Capacitor Clock 1 |
33 |
IQphi1 -- Kernel
Clock 1 |
9 |
Vbn -- NMOS bias
voltage |
32 |
IQphi1' --
Complement of IQphi1 |
10 |
Vcp -- PMOS
cascode bias voltage |
31 |
IQphi2 -- Kernel
Clock 2 |
11 |
Vbp -- PMOS bias
voltage |
30 |
IQphi2' -- complement of IQphi2 |
12 |
Vclamp --
Measuring voltage for array |
29 |
IQphi3 -- Kernel
Clock 3 |
13 |
BQIout -- Beam
Quality output current |
28 |
IQphi3' --
complement of IQpih3 |
14 |
BQref -- Beam
Quality reference voltage |
27 |
|
15 |
VDD |
26 |
|
16 |
SRinput -- Shift
register input |
25 |
|
17 |
SRphi2' --
complement of SRpih2 |
24 |
|
18 |
SRphi2 -- Shift
register clock 2 |
23 |
|
19 |
SRphi1' --
complement of SRphi1 |
22 |
|
20 |
|
21 |
|
Pixel Simulation
The pixel performs as expected, as approximating the photocurrent as 25 nA it is evident that the pixel accumulates charge as expected, and discharges this stored charge in 400 ns. This settling time is the limiting factor in the beam quality computations to be performed.
Beam Quality Simulation
The beam quality circuit performs almost as expected; however, because of the early effect, it does not achieve an ideal quadratic relationship between inupt voltage and input current.
Note that the shift registers, and beam quality components LVS without any problem; however, because the pixel has a floating source, it, and consequently the array, cannot be LVS'ed with the techfiles we had to work with.
Potential new pixel design
Analog Integrated Circuit Design
D. J. Johns and K. Martin
Wiley, 1997
Design of Analog-Digital VLSI Circuits for Telecommunications
J. E. Franca and Y. Tsividis, Eds.
Prentice-Hall, 1994
VLSI Design Techniques for Analog and Digital Circuits
Randall Geiger, Phillip Allen, Noel Strader
McGraw-Hill