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Our chip implements a CDMA encoder/decoder. The encoder takes in a
signal and a pseudorandom (pn) code and multiplies them together. The decoder tries to
decode the signal. First the signal is multiplied by the pn, and then
it is checked to see whether the input is actually correlated (if there is
a signal present). If there is no signal present, the phase is advanced.
Once it finds a signal it tests the classification of the signal:early or
late. If the signal is early the phase needs to be postponed until later.
If the signal is late, the next signal is detected. The signal detected
adjusts with the early/late phase and then filters out the original signal
from the product of the signal and the pn code. The code acquisition has
a 10KHz bandwith with 1.25MHz pn codes.
The group took an analytical approach to solving the problem. First MATLAB simulations were used in order to discern the different characteristics for the circuit, mainly for the 10 KHz cut-off frequency. The group then worked together on designing and researching optimal circuits to compile together for a complete circuit. After some experimentation with an operational amplifier, translinear conductor, integrator, multiplexor, D flip flip, comparator, and phase locked loop, the group decided to use the following components:multiplexor, rectifier, low pass filter, delay, and counter.
Our chip is designed to take in a signal and encode it. Our system takes in a signal and multiples it with a pn code. This combination signal is then filtered with a low pass filter with cut-off frequency 10 MHz. The signal is then rectified in order to obtain an absolute value for the circuit, ultimately testing it's power. The signal is then sent through the low pass filter again and out to digital logic. The digital logic exists to match the pn code to the existing signal. The signal's status is discerned as follows:if the on-time signal is below the threshold, the phase is moved later. If the the on-time signal is above the threshold, there are different cases: 1) if the amplitude of the "early" signal is larger than the "late" sigmal, advance the signal; 2) conversely if "late" is greater than "early" then delay the signal, and 3) if they are comparable, take no action as the signal is locked on.
By using MATLAB, we have discerned that our circuit will lock on to the
Using Cadence simulations, the integration of the signal when the pn code is matched yields a value of 3 volts for the pilot signal and 2.3 V for the sin wave (this is on a 1-3 Volt swing). For a non-locked-on signal that is further than the Tc (chip time), the integration result was 1.9 volts for the sin wave.
The simulation of these parts parallels the MATLAB simulation.
Furth, Paul M. and Andreas G. Andreou. "Translinear Transconductor Design
for Cochlear Filter Banks" 1997.
Viterbi, Andrew J. CDMA Principles of Spread Spectrum Communication New York: Addison-Wesley Publishing Company, 1995.