520.490 Analog and Digital VLSI Systems

Second-Order Delta-Sigma Modulator with Multi-bit Feedback

Erin Moyer

epm1@jhu.edu

Edward Tang

ect1@jhu.edu

Seyed Pooya Hejazi

sph@jhu.edu


Milutin Stanacevic, Graduate Advisor

miki@jhu.edu

Top view of the chip layout, excluding padframe

 

Objectives

 

Delta Sigma modulation is a technique used to generate a coarse estimate of a signal using a small number of quantization levels and a very high sampling rate.  The finite number of quantization levels introduces “quantization” noise into the system, and a special characteristic of a Delta Sigma modulator is its ability to “push” this noise into higher frequencies.  This allows the use of DSP techniques to “decimate” the sequence and produce a more precise bit representation of the input.  The objective of this chip is to improve a simple, first-order, single-bit delta sigma modulator by stepping up to a second-order system with multi-bit feedback in order to improve the noise-shaping characteristics and reduce quantization noise. 

Specifications

 

The initial target speed for the system is thirty-two times the Nyquist rate of a signal in the audible spectrum (32 * 40Khz = 1.28 MHz).  Throughout the design process, the objective was the keep the hardware components as simple, fast, and yet accurate as possible, to minimize complexity and real estate on the chip die.  Integrators were implemented using a simple, cascaded inverting amplifier and the double-correlated sampling technique.  It was decided that a three-bit quantizer would give the benefits of multi-bit feedback without increasing the complexity too significantly, and the quantizer was implemented with an ADC and DAC.  More specifically, a flash ADC was chosen due to the minimum half-cycle delay of the output, and a charge-scaling DAC was chosen due to the ease of implementing the negative feedback by injecting charge into the input node of each inverting amplifier.  Five clocks and a three-bit shift register were used to synchronize the various components of the system and to ensure proper operation (see below for a more detailed discussion of the clocks). 

 

The final objective of the project is to lay out the system using the Cadence tools.  The process used is the AMI05 (0.5 micron), polysilicon, multi-metal, sub-micron process (metal1, metal2, metal3).  The design rules followed for the layout were provided by the MOSIS sub-micron process (www.mosis.org).

 

 

 

 

 

 

 

 

 

1

 

40

 Vdd – supply voltage (5V)

2

 

39

 

3

 

38

 

4

 

37

 

5

 Phi2

36

 

6

 Phi2’

35

 

7

 Phi1

34

 

8

 Phi1’

33

 

9

 Phi3 – (Phi1 w/ earlier neg. edge)

32

 

10

 Phi3’

31

 

11

 In – input to DSM 0-4.4V for Vdd = 5V

30

 Gnd – ground

12

 Phi5 – (Phi1 delayed by one period)

29

 

13

 Phi4 – (Phi2 delayed w/ later pos. edge)

28

 

14

 Phi4’

27

 

15

 Phi5’

26

 

16

 Iin – biasing current for inverting amp (25uA)

25

 Bit2 – output bit (MSB)

17

 Out – input approximation (unquantized)

24

 Bit1 – output bit

18

 Vref – ref voltage for DAC and ADC (4.2V)

23

 Bit0 – output bit (LSB)

19

 

22

 

20

 

21

 

 

 

A Note about the Clocks

 

Phi1 and Phi2 are the basic clocks needed for the delta sigma modulator.  Phi3 is used to eliminate the noise feed-through that occurs on the negative edge of Phi1.  The purpose of Phi4 is to allow the inverting amplifier of the first integrator to settle before the input to the second integrator is taken.  Finally, Phi5 is used for startup purposes to prevent the second integrator from saturating (i.e. to keep the second integrator from accumulating data too early).

 

 

 

 

Results

 

Individually, all the components of the system operate properly at the required speed.  Furthermore, when the components are put together the overall system also operates correctly at the initial target speed (and more).  The system is stable and performs quite well for the indicated frequency range (specified in the specifications section) and beyond.  The input voltage range is from zero to 4.4 volts (for our supply voltage of 5 volts), and the output of the system is a parallel stream of three-bit words (pins: Bit0, Bit1, Bit2).  To verify that the system is indeed functioning properly, we also considered the output of the second integrator (the unquantized approximation of the input signal) as an output (pin:out).  The plot below illustrates both the bit output and the verification output.

 

Furthermore, a layout for the system was successfully constructed.  The LVS verification validated the match between the working schematic and the chip, and the system was attached to the pad frame.  An important consideration during the design of the layout was the separation between the digital and analog components of the system.  To minimize the digital noise interference with the analog lines, the digital components of the system (ADC, shift register, DAC), as well as the digital bit output, were kept away from the mainly analog lines in the integrator component.  More exactly, the integrator is on the bottom left, while the ADC, shift register, and DAC are together to the top and right.

 

It should also be noted that the size of the shift register is relatively small (1000 X 600 lambda) compared to the overall size of the pad frame/chip (4000 X 4000 lambda).  The extra room on the chip can be used for digital components that serve three main purposes: 1) to cut down the number of clocks needed from external pins (by using inverting logic and digital delays) 2) to do digital signal processing on the parallel bit output of the delta sigma modulator for more precise A/D conversion 3) to provide the control logic in case multiple delta sigma modulators are on the chip (example: organizing a single, serial input for multiple delta sigma modulators).

 

 

 

 

 

 

 

 

References

 

Candy, James C.; Temes, Gabor C.: Oversampling Delta-Sigma Data Converters; Theory Design and Simulation; IEEE Press 1992

 

Geiger, R. L.; Allen, Phillip E.; Strader, Noel R.: VLSI Design Techniques for Analog and Digital Circuits; McGraw-Hill Inc. 1990