520.490 Analog and Digital VLSI Systems

A High-Speed, 8-bit Delta-Sigma Analog-to-Digital Converter Array

Farhan Adil, Andrew Chu and Grant Mulliken

bigf@jhu.edu, chewie@jhu.edu, gmullike@bme.jhu.edu

[Layout of Chip]




An array of 128 delta-sigma ADCs was designed to interface with a vector matrix-multiplier designed by Roman Genov that feeds in analog voltages to be sampled and converted to an 8-bit digital value in under 10 microseconds.  The team initially met with advisors Roman Genov and Gert Cauwenberghs to define a block diagram and the mathematical theory underlying  the A/D's operation.  A top-down approach was then taken to further define the circuit elements of each block.  Before proceeding further and integrating individual circuit blocks together, MATLAB was used to model the theory of operation in terms of the mathematical model derived previously.  Following successful modeling in MATLAB, the schematics of the system were then assembled and tested using Cadence’s simulator. Upon successful simulation of the schematics, layout and LVS verification were completed for all circuits.        



The A/D is designed to output an 8-bit digital value in 25 cycles instead of the typical 28 cycles required for first-order single-bit delta-sigma conversion.  This is accomplished in two steps.  First, the four higher-order bits (MSB) are computed in 16 cycles (24 cycles), performing a 4-bit delta-sigma conversion on the analog input.  Next, the resulting residue, represented by the voltage on the integrator after the first 16 cycles, is then fed back to the input for a second 16 cycles.  The subsequent four bits represent the remaining four lower-order bits of the 8-bit output value (LSB).  Thus, the entire 8-bit conversion is performed in 25=32 cycles instead of 28=256 cycles, yielding an 8-fold increase in speed without requiring a more complicated second-order modulator and comb decimator. 

[Block Diagram]

***Fed back for LSBs

128 of the A/Ds are arranged in a row-parallel fashion, aligned with 128 of the respective rows of the matrix multiplier.  The analog input ranges from 2 to 4 volts.  All simulations were run at 5MHz, ensuring a valid digital output in less than the 10 microseconds as required by the matrix multiplier.  Both the delta-sigma A/D converter and all digital control circuitry are driven by a 3-phase, non-overlapping clock. 


Basic operation is as follows:

1.      The analog value is fed into a sample/hold circuit and is passed into the input of the delta-sigma modulator, “X”, as seen in the above diagram.

2.      The reference voltage is subtracted from the input and the difference is  then accumulated on the storage capacitor of the accumulator, denoted as “ς” in the diagram. 

3.      This accumulated value, “u”, is then quantized via a one-bit comparator, producing a unary output, “Y”, for each cycle which is then counted and stored by a 4-bit ripple counter.

4.      Following 16 cycles, “u” is then fed back to the sample/hold, the counter is cleared and the data is latched and sent off-chip, and steps 2-3 are repeated for the next 4 LSBs over 16 more cycles. 

5.        Steps 1-4 are then repeated every 10 microseconds for subsequent analog inputs.

 **Note: See the appendix for more detailed equations explaining circuit behavior.




VrefInit - clock to init D/A, input




SHCtrl - clock for S/H, input




INT1 - non-overlapping clock: Integrating switch: allows integrator to output accumulated value to comparator, input




INT2 - non-overlapping clock: Switches in Vin from S/H, input


 Ibias – Bias current for inverting amplifier


INT3 - non-overlapping clock: determines Vref for next integration cycle, input


Vin – input for A/D row (test pin for 1st row), output


Precharge1 - non-overlapping clock:  precharge inverting amp, input


Output – unary output (test pin for 1st row), output 


Precharge2 - non-overlapping clock: allows input of Vef, input


LatchOut – signal to enable digital latch for scan out (test pin for 1st row), output 


VDD-5V, input


FeedbackSel - signal to enable residue feedback (test pin for 1st row), output


GND, input


VirtGndComp – node of compator where virtual gnd is made (test pin for 1st row), output


+Vref – high reference voltage for A/D (4.0625 V), input


VirGndAcc – node of inv_amp where virtual gnd is made (test pin for 1st row), output


-Vref – low reference voltage for A/D (2.0625 V), input


VrefFeedback - reference voltage for feedback of residue (test pin for 1st row), output 


+V1 - reference voltage for residue feedback (1.0625 V), input


Vref - reference voltage for A/D row slice (test pin for 1st row), output 


-V1 - reference voltage for residue feedback (3.0625 V), input


CompOut1 - voltage out on comparator (test pin for 1st row), output


Vcomp - reference point for comparator (3 V), input


Vstore - voltage on comparator (test pin for 1st row), output  


Vin1- Analog Voltage In, input


OutputEnable - signal to specify when to read digital outputs, output


Vin2- Analog Voltage In, input


DigitalOut4 - 4th bit of digital, output  


Vin3- Analog Voltage In, input


DigitalOut3 - 3rd bit of digital, output 


Vin4- Analog Voltage In, input


DigitalOut2 - 2nd bit of digital, output 


ScanClk1 – clock to perform serial output of 128 4-bits of each row A/D  input


DigitalOut1 - 1st bit of digital, output 


ScanClk2 - non-overlapping clock (3-phase scan clocks), input


ScanClk3 - non-overlapping clock (3-phase scan clocks), input

Input Clocks

Input Voltages

Output Pins

Test Output Pins




            The results obtained from Cadence show that the A/D system has 7-bit output precision.  In the simulation plots given below, we have provided results for two different analog input voltages, 2.5V and 3.4V.  A plot of the clocking scheme is also given.  The 3.4 V input yields a binary output of ‘b10110010.  Our data was 7-bit accurate as the expected binary output, denoted by signals D0-D3, was ’b10110011.  At least 7-bit precision was seen for all inputs in our 2-4 V range.  8-bit precision was seen in multiple cases as in the case where the input was 2.5V.  

The 1-bit error is due to charge injection noise occurring on the accumulator capacitor.  The voltage on this capacitor must remain extremely accurate for the resulting voltage to give 4 bits accuracy for the lower order bits (second 16 cycles).  Possible solutions to this problem would be to use dummy switches to reduce the charge injection noise, or to use larger capacitors.  Both alternatives are currently being explored. 

            The feedback of residual voltage is not limited by the number of bits or the number of feedback interations.  Other feedback schemes are also viable.  For example, 32 cycles can be run to obtain a 5-bit output, from which the residue voltage can be fed back to obtain another 5 bits, thereby obtaining 10 bits in 64 cycles instead of the typical 1024.  Likewise, another option would be to run 8 cycles to get 3 bits, and repeat this 3-bit conversion two more times to obtain an overall 9-bit output in 24 cycles, instead of 512.  Charge injection noise has proven to only affect the LSB, thus these iterations should have greater than 7 bits accuracy. 

The clocking scheme can be seen in the third simulation plot.   Precharge1/2 constitute the first phase, INT1/2 the second phase, and INT3 the third.  INT0 is derived from Precharge1.   RST, VefInit and SHCtrl are all sent in from off-chip as well.

            In preparation for fabrication, our near-term goals are to fine-tune the A/D to obtain 8-bit resolution, optimize the clocking circuitry and integrate the row-parallel  A/Ds successfully with Roman’s matrix multiplier.  Final testing will occur later this spring.


Simulated waveforms (for 2.5V and 3.4V DC inputs)

[Clock Timing Diagram]

Clock timing diagram


1.    Gert Cauwenberghs and Roman Genov, Dept. of Electrical and Computer Engineering, Johns Hopkins University.

2.    Candy, James C.; Temes, Gabor C.: Oversampling Delta-Sigma Data Converters; Theory Design and Simulation; IEEE Press 1992



Appendix: Calculations and Mathematical Theory


All variables correlate with nodes on block diagram given above, x is the analog input, u is the accumulated voltage, and y is the output. x' is the integration residue at the end of the MSB sequence, resampled at the input for the LSB sequence.   a-scaling is due to a ratio in the two capacitor sizes used in the accumulator.