bigf@jhu.edu,
chewie@jhu.edu,
gmullike@bme.jhu.edu
An array of 128 deltasigma ADCs
was designed to interface with a vector matrixmultiplier designed by Roman
Genov that feeds in analog voltages to be sampled and converted to an 8bit
digital value in under 10 microseconds.
The team initially met with advisors Roman Genov and Gert Cauwenberghs to
define a block diagram and the mathematical theory underlying the A/D's operation. A topdown approach was then taken to further
define the circuit elements of each block.
Before proceeding further and integrating individual circuit blocks
together, MATLAB was used to model the theory of operation in terms of the
mathematical model derived previously.
Following successful modeling in MATLAB, the schematics of the system
were then assembled and tested using Cadences simulator. Upon successful
simulation of the schematics, layout and LVS verification were completed for
all circuits.
The A/D is designed to output an 8bit digital value in 2^{5} cycles instead of the typical 2^{8} cycles required for firstorder singlebit deltasigma conversion. This is accomplished in two steps. First, the four higherorder bits (MSB) are computed in 16 cycles (2^{4} cycles), performing a 4bit deltasigma conversion on the analog input. Next, the resulting residue, represented by the voltage on the integrator after the first 16 cycles, is then fed back to the input for a second 16 cycles. The subsequent four bits represent the remaining four lowerorder bits of the 8bit output value (LSB). Thus, the entire 8bit conversion is performed in 2^{5}=32 cycles instead of 2^{8}=256 cycles, yielding an 8fold increase in speed without requiring a more complicated secondorder modulator and comb decimator.
***Fed back for LSBs
128 of the A/Ds are arranged in a rowparallel fashion, aligned with 128 of the respective rows of the matrix multiplier. The analog input ranges from 2 to 4 volts. All simulations were run at 5MHz, ensuring a valid digital output in less than the 10 microseconds as required by the matrix multiplier. Both the deltasigma A/D converter and all digital control circuitry are driven by a 3phase, nonoverlapping clock.
Basic operation is as follows:
1. The analog value is fed into a sample/hold circuit and is passed into the input of the deltasigma modulator, X, as seen in the above diagram.
2. The reference voltage is subtracted from the input and the difference is then accumulated on the storage capacitor of the accumulator, denoted as ς in the diagram.
3. This accumulated value, u, is then quantized via a onebit comparator, producing a unary output, Y, for each cycle which is then counted and stored by a 4bit ripple counter.
4. Following 16 cycles, u is then fed back to the sample/hold, the counter is cleared and the data is latched and sent offchip, and steps 23 are repeated for the next 4 LSBs over 16 more cycles.
5.
Steps 14 are then repeated every 10 microseconds for
subsequent analog inputs.
**Note: See the appendix for more detailed equations
explaining circuit behavior.
1 
VrefInit  clock to init D/A, input 
40 

2 
SHCtrl  clock for S/H, input 
39 

3 
INT1  nonoverlapping clock: Integrating switch: allows
integrator to output accumulated value to comparator, input 
38 

4 
INT2  nonoverlapping clock: Switches in Vin from S/H, input 
37 
Ibias Bias current for inverting amplifier 
5 
INT3  nonoverlapping clock: determines Vref for next
integration cycle, input 
36 
Vin input for A/D row (test pin for 1^{st} row),
output 
6 
Precharge1  nonoverlapping clock: precharge inverting amp, input 
35 
Output unary output (test pin for 1^{st} row), output 
7 
Precharge2  nonoverlapping clock: allows input of Vef, input 
34 
LatchOut signal to enable digital latch for scan out
(test pin for 1^{st} row), output 
8 
VDD5V, input 
33 
FeedbackSel  signal to enable residue feedback (test pin
for 1^{st} row), output 
9 
GND, input 
32 
VirtGndComp node of compator where virtual gnd is made
(test pin for 1^{st} row), output 
10 
+Vref high reference voltage for A/D (4.0625 V), input 
31 
VirGndAcc node of inv_amp where virtual gnd is made
(test pin for 1^{st} row), output 
11 
Vref low reference voltage for A/D (2.0625 V), input 
30 
VrefFeedback  reference voltage for feedback of residue
(test pin for 1^{st} row), output 
12 
+V1  reference voltage for residue feedback (1.0625 V), input 
29 
Vref  reference voltage for A/D row slice (test pin for 1^{st}
row), output 
13 
V1  reference voltage for residue feedback (3.0625 V), input 
28 
CompOut1  voltage out on comparator (test pin for 1^{st}
row), output 
14 
Vcomp  reference point for comparator (3 V), input 
27 
Vstore  voltage on comparator (test pin for 1^{st}
row), output 
15 
Vin1 Analog Voltage In, input 
26 
OutputEnable
 signal to specify when to read digital outputs, output 
16 
Vin2 Analog Voltage In, input 
25 
DigitalOut4  4^{th} bit of digital, output 
17 
Vin3 Analog Voltage In, input 
24 
DigitalOut3  3^{rd} bit of digital, output 
18 
Vin4 Analog Voltage In, input 
23 
DigitalOut2  2^{nd }bit of digital, output 
19 
ScanClk1 clock to perform serial output of 128 4bits of
each row A/D input 
22 
DigitalOut1  1^{st} bit of digital, output 
20 
ScanClk2  nonoverlapping clock (3phase scan clocks), input 
21 
ScanClk3  nonoverlapping clock (3phase scan clocks), input 
Input Clocks
Input Voltages
Output Pins
Test Output Pins
The results obtained from Cadence show that the A/D system has 7bit output precision. In the simulation plots given below, we have provided results for two different analog input voltages, 2.5V and 3.4V. A plot of the clocking scheme is also given. The 3.4 V input yields a binary output of b10110010. Our data was 7bit accurate as the expected binary output, denoted by signals D0D3, was b10110011. At least 7bit precision was seen for all inputs in our 24 V range. 8bit precision was seen in multiple cases as in the case where the input was 2.5V.
The 1bit error is due to charge injection noise occurring on the accumulator capacitor. The voltage on this capacitor must remain extremely accurate for the resulting voltage to give 4 bits accuracy for the lower order bits (second 16 cycles). Possible solutions to this problem would be to use dummy switches to reduce the charge injection noise, or to use larger capacitors. Both alternatives are currently being explored.
The feedback of residual voltage is not limited by the number of bits or the number of feedback interations. Other feedback schemes are also viable. For example, 32 cycles can be run to obtain a 5bit output, from which the residue voltage can be fed back to obtain another 5 bits, thereby obtaining 10 bits in 64 cycles instead of the typical 1024. Likewise, another option would be to run 8 cycles to get 3 bits, and repeat this 3bit conversion two more times to obtain an overall 9bit output in 24 cycles, instead of 512. Charge injection noise has proven to only affect the LSB, thus these iterations should have greater than 7 bits accuracy.
The clocking scheme can be seen in the third simulation plot. Precharge1/2 constitute the first phase, INT1/2 the second phase, and INT3 the third. INT0 is derived from Precharge1. RST, VefInit and SHCtrl are all sent in from offchip as well.
In preparation for fabrication, our nearterm goals are to finetune the A/D to obtain 8bit resolution, optimize the clocking circuitry and integrate the rowparallel A/Ds successfully with Romans matrix multiplier. Final testing will occur later this spring.


Simulated waveforms (for 2.5V and 3.4V DC inputs)
Clock timing diagram
1.
Gert Cauwenberghs and Roman Genov, Dept. of Electrical and
Computer Engineering, Johns Hopkins University.
2.
Candy, James C.; Temes, Gabor C.: Oversampling
DeltaSigma Data Converters; Theory Design and Simulation; IEEE Press 1992
Appendix: Calculations and Mathematical Theory
All variables correlate with nodes on block diagram given above, x is the analog input, u is the accumulated voltage, and y is the output. x' is the integration residue at the end of the MSB sequence, resampled at the input for the LSB sequence. ascaling is due to a ratio in the two capacitor sizes used in the accumulator.
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