520.490 Analog and Digital VLSI Systems

Algorithmic Partial Analog to Digital Converter

Wesley Smith, Burt Ross
Graduate Advisor: Roman Genov

wess@jhu.edu

burt@jhu.edu

roman@jhu.edu

 

 

 Layout of the algorithmic partial ADC, for massively parallel quantization along rows of computational or sensor arrays.
One channel is shown; peripheral wiring is added for extraction and LVS purposes.

 

Objectives

 

The need for a high speed, yet small in size, ADC requires a novel approach.  Using an algorithmic method, an ADC can be built from small, reliable components arranged in the proper fashion.  This ADC is designed specifically to hand analog outputs of a certain type: those that result from analog matrix multiplication, giving a sort of binary weight to the analog outputs [1].

Specifications

 

The algorithmic partial ADC designed for this project takes an input (Vin) within a range of 0 to 2.5 V every microsecond and converts it into two output bits.  The ADC, itself, is divided into two main stage, which are nearly identical.  Each takes one microsecond to perform its calculations: outputting a bit and passing on the residue to the other stage.  Each stage can be broken down into three parts: the input stage, the mid stage, and the comparator stage.  The input stage is nothing more than a series of MUXs connected to the proper clocks.  The mid stage is a cascoded inverting amplifier paired, with a switch, and either a switch or a two input MUX.  Fianlly, the comparator stage is three inverting amplifiers connected in series with a switch and a capacitor.

 

The first stage takes the new input and adds it to the residue of the second stage, performs a comparison, and calculates the residue to be passed on to the second stage.  Its output bit is a zero if the sum of the residue and new input are below Vref + (2.5 V) and a one if the sum is above Vref+.  This bit then determines the residue.  If the bit is low, the sum is the residue.  If the bit is high, the residue is the sum less Vref+.

 

The second stage is identical in operation except for its transfer function.  It outputs a zero when the input (stage one's residue) is below Vref+/2 (1.25 V) and a one if the input is above Vref+/2.  This bit then determines the output residue.  The residue is the input for input less than Vref+/2 for a low bit and the input less Vref+/2 for a high bit.

 

For any given input (Vin), two bits are output.  The bit from the first stage is of one binary weight greater than that of the second stage, so a summing operation will need to be performed to find the true binary word.

 

Example of Bit outputs (first index is input, second index is bit #)

  2^n 2^n-1 2^n-2

2^n-3

Vin 1:

D11

D22

 

 

Vin 2:

 

D21

D22

 

Vin 3:

 

 

D31

D32

  

 

1

 

40

 

2

 

39

 

3

 

38

Out1 -- Stage 1 residue

4

 

37

Out2 -- Stage 2 residue

5

Vin -- input voltage

36

 

6

Vref+ -- upper reference voltage (2.5 V)

35

Vdd

7

Vref- -- lower reference voltage (1 V)

34

D1 -- stage 1 bit

8

Vm -- comparison voltage (1.25 V)

33

D2 -- stage 2 bit

9

 

32

 

10

 

31

Vref -- 

11

Phi C -- cycle clock

30

 

12

Phi 4 -- input clock

29

Cap_Node -- 

13

Phi 3 -- comparison voltage clock

28

Cap_Node2 -- 

14

Phi 2 -- residue clock

27

Bit_In2 -- stage 1 comparator stage cap voltage

15

Phi 1 -- comparator clock

26

Bit_In1  -- stage 2 comparator stage cap voltage

16

 

25

 Gnd

17

Vbp -- pmos bias (3.8 V)

24

 Cap2-2 -- voltage of stage 2 lower cap

18

Vcp -- cascode pmos voltage (3.6 V)

23

 Cap2-1 -- voltage of stage 2 upper cap

19

Vcn -- cascode nmos voltage (1.6 V)

22

 Cap1-2 -- voltage of stage1 lower cap

20

 

21

 Cap1-1 -- voltage of stage 1 upper cap

 

Results

          Stage 1 Simulation

 

 

In this simulation, the input sum (Vin plus stage 2 residue) was less than Vref+, so the output bit D1 was low.  The bit is valid when Phi 3 goes high.  When Phi 2 goes high, the residue calculation is valid with the value of Out1 being the residue.  The works fine within the 1 microsecond time constraint and could easily be sped up 200ns.

 

Stage 2 Simulation

 

In this simulation, the input was greater than Vref+/2, making the output bit (D2) high.  Like in stage 1, the bit is valid during Phi 3 and the residue is valid during Phi 2.

References

[1] "Charge-Mode Parallel Architecture for Matrix-Vector Multiplication," R. Genov and G. Cauwenberghs, IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 48 (10), pp. 930-936, Oct. 2001.

[2] Analog Integrated Circuit Design, D. J. Johns and K. Martin, Wiley, 1997.

[3] VLSI Design Techniques for Analog and Digital Circuits Randall Geiger, Phillip Allen, Noel Strader, McGraw-Hill, 1994.