520.490 Analog and Digital VLSI Systems
Multiple Sampling Wide Dynamic Range
Imager with
Successive Approximation Analog to Digital Converter
Alexandra Heron, Francisco Tejada,
Sara Woo
akh2@jhunix.hcf.jhu.edu
ft1@jhu.edu
swoo@jhu.edu
View of chip layout inside of pad frame
Objectives
The purpose was to build a wide dynamic range imager using a voltage mode
APS pixel. The chip has auto and external control of integration time, so
the chip adapts to changes in lighting conditions automatically. The chip
will have the option of obtaining digital or analog output, therefore it is
necessary to put an analog to digital converter onboard. Ideally the
point is to make a complete system on a single chip.
Specifications
To gain dynamic range we implemented a multiple sampling technique [8]. Normal dynamic range is considered to be around 70dB, however we hope to increase that number to 100dB or greater.� However, we will not be able to determine this value until testing.� Our chip reads two rows per cycle, so for the 64 X 64 array we access 128 rows.� This technique gives multiple integration times for each pixel, which will be combined off chip. Of the two integration times, the longer one will pick up dark parts of the image and the shorter time will pick up the brighter part. The double readout scheme is shown below:
Double Read Out
�
These values will be output in a column parallel fashion to the correlated
double sampling unit that will reduce the fixed pattern noise and DC offset
inherent in the pixel outputs.� It also
doubles as a storage location for the data.�
After this step the data is output to the ADC. �There will be 16 ADC�s on chip and each ADC
will convert 4 columns of data.� Due to
the large amount of data we need a video rate ADC.� From the ADC, the data, now in digital form, will go off
chip.� Below is a general architectural
diagram of the chip:
Overall System Architecture
From the architecture above, see that the row select scans down the array, and is sent to the correlated double sampling column select. From this point the data goes to three places. It goes off-chip as analog output, it gets sent to the multiple ADC's to get changed into digital information and then output off-chip and it goes to the auto control unit where it will be evaluated to see if the integration times need to be adjusted. After the entire frame has been scanned the integration time is adjusted if necessary and then the scan begins again. Every time the scan begins the bit pattern being used to do the row select is also output from the chip so that the user can know the relation between the integration times, something that must be known to recombine the two pixel values.
Pin Out Scheme
|
1 |
A
Vdd: 5V for analog circuitry |
40 |
Vref2:
Reference voltage for CDS |
|
2 |
A
Gnd: Gnd for the analog circuitry |
39 |
D
Vdd: 5V for digital circuitry |
|
3 |
Analog
Out 0 |
38 |
D
Gnd: Gnd for digital circuitry |
|
4 |
Analog
Out 1 |
37 |
Reset:
Chip reset pin |
|
5 |
Analog
Out 2 |
36 |
Count
In: Test pin for counter |
|
6 |
Analog
Out 3 |
35 |
Count
Out: test pin for counter |
|
7 |
Digital
Out 0 |
34 |
CDS
In: test pin for CDS |
|
8 |
Digital
Out 1 |
33 |
ADC
In: test pin for ADC |
|
9 |
Digital
Out 2 |
32 |
ADC
On/Off: Turns ADC on or off |
|
10 |
Digital
Out 3 |
31 |
Auto control On/Off: Turns Auto Control |
|
11 |
Digital
Out 4 |
30 |
Delta
Out: Sends out the bit row select bits |
|
12 |
Digital
Out 5 |
29 |
Delta
In: External input for row select |
|
13 |
Digital
Out 6 |
28 |
Control
Input: Input for control circuit |
|
14 |
Digital
Out 7 |
27 |
Control
Output: Test pin for control circuit |
|
15 |
CDS/ADC
Vdd: 5V for CDS and ADC |
26 |
|
|
16 |
CDS/ADC
Gnd: Gnd for CDS and ADC |
25 |
|
|
17 |
V
bias: Bias voltage for ADC |
24 |
|
|
18 |
Vref:
Reference voltage for ADC |
23 |
|
|
19 |
VH:
Comparison voltage for Auto Control |
22 |
|
|
20 |
VL:
Comparison voltage for Auto Control |
21 |
|
Results
We simulated the range of readouts from our pixel to be between 0V and 3V, which we used to limit the range of our ADC.� With this range the ADC has a resolution of approximately 11.7mV.� The limiting factor of our scanning speed was how quickly the ADC could convert the pixel data.� We designed our ADC run at approximately 10Mhz.� With 16 of them on chip, this should not be a factor in our scanning speed.� Below is a chart detailing what we have accomplished, and what parts remained to be finished.� The auto control has been simulated on a small scale. Every part works in a 64-bit manner, but due to the time needed to simulate a 64-bit schematic of the whole thing it has not been done.� All of the individual parts have been rigorously tested to make sure that they function properly.� The CDS circuit has also been tested very well.� We have run a multitude of values through it and checked for proper results.� We basically have everything working, we just have not had time to put the whole thing together and run a simulation of the entire chip.� The timing of the chip has been planned out; we have not however had time to actually implement the circuitry yet.� We plan for all control circuits to be on chip, this includes clocks and timing circuitry.
Accomplishments
|
Module |
Schematic |
Simulation |
Layout |
LVS |
|
Auto Control 1 bit |
� |
� |
� |
� |
|
Auto Control 64 bit |
|
|
� |
|
|
CDS 1 bit |
� |
� |
� |
� |
|
CDS 64 bit |
|
|
� |
|
|
ADC unit |
� |
� |
� |
� |
|
ADC 16 units |
|
|
� |
|
|
Control / Timing |
|
|
|
|
References
[1] B. Pain, G. Yang, M. Oritz, K. McCarty, B. Hancock, J. Heynssens, T. Cunningham, C. Wrigley, and C. Ho, "A Single-chip Programmable Digital CMOS Imager with enhanced Low-light Detection Capability," 13th International Conference on VLSI Design - January 2000, pp 342-347.
[2] D.X.D. Yang, A. El Gamal, B. Fowler, H. Tian, "A 640 x 512 CMOS Image Sensor with Ultrawide Dynamic Range Floating-Point Pixel-Level ADC," IEEE Journal of� Solid-State Circuits, Vol. 34, No. 12, December 1999, pp 1821-1833.
[3] Fossum, Eric R, "CMOS Image Sensors: Electronic Camera-On-A-Chip," IEEE Transactions on Electron Devices, Vol. 44, No. 10, October 1997, pp. 1689-1698.
[4] Fossum, Eric R, "Digital Camera System on a Chip, " May-June 1998 IEEE
[5] M. Schanz, C. Nitta, A. Bubmann, B.J. Hosticka, And R.K. Wertheimer, "A High-Dynamic-Range CMOS Image Sensor for Automotive Applications," IEEE Journal of Solid-State Circuits, Vol. 35, No. 7, July 2000, pp. 932-938.
[6] McIlrath, Lisa G, "A Low Power, Low Noise, Ultra-Wide Dynamic Range CMOS Imager with Pixel-Parallel A/D Conversation," 2000 Symposium on VLSI Circuits Digest of� Technical Papers, pp 24-26.
[7] O. Schrey, R. Hauschild, B.J. Hosticka, U. Lurgel, M. Schwarz, "A Locally Adaptive CMOS Image Sensor with 90dB Dynamic Range," 1999 IEEE International Solid-State Circuits Conference, pp 310-311, 472.
[8] Yadid-Peche, Orly and Fossum, Eric R, "Wide Intrascene Dynamic Range CMOS APS Using Dual Sampling," IEEE Transactions on Electron Devices, Vol. 44, No. 10, October 1997, pp. 1721-1723.
[9] C. H. Aw, B. A. Wooley, �A 128 x 128-Pixel Standard-CMOS Image Sensor with Electronic Shutter� IEEE Journal of Solid-State Circuits, Vol. 31, No. 12, December 1996. pp 1922-1930
[10] Z. Zhou, B. Pain, E. Fossum, "A CMOS Imager with On-Chip Variable Resolution for Light-Adaptive Imaging," Digest of Technical Papers, February 6, 1998.
[11] Z. Zhou, B. Pain, E. Fossum, �CMOS Active Pixel Sensor with On-Chip Successive Approximation Analog-To-Digital Converter,� IEEE Transactions on Electron Devices, Vol. 44, No.10, October 1997. pp1759-1763.
[12] M.C. Gupta, �Handbook of Photonics�, CRC Press, New York.� pp 301-303
[13] S.M. Sze. �Physics of Semiconductor Devices� Second Edition, John Wiley & Sons, New York.� pp 749-753.
[14]
R. Jacob Baker, Harry W. Li, David E. Boyce,� �CMOS Circuit Design, Layout, and Simulation� IEEE Press Series
on Microelectronic Systems. pp 686-699