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Successive Approximation ADC
Good compromise between size, speed and power consumption.
Performs multiple comparisons using a binary search algorithm.
Inputs into system: reference voltage of 3V and photo voltage.
Linear conversion time - N clock cycles to complete N-bits.
Geometrically sized capacitor array samples the input voltage therefore no need for an external S/H.
Notes:
Low power consumption: only uses capacitors, switches and a comparator
Comparator delay time 2 ns - Completes one 8-bits conversion every 95nS – 10MHz
8 bits of accuracy - Smallest capacitor 23.75fF, total capacitance 6.08pF
Realistically, capacitor mismatch could be an issue- Approximately 700l X 100l for each ADC