520.490 Analog and Digital VLSI Systems

Support Vector Machine with On-Chip Training

Mihir Naware  (mnaware@bme.jhu.edu) , Zaki Yahya (zaki@jhu.edu)

Graduate Student Advisor - Shantanu Chakrabartty.

Fig 1 : Complete layout within the padframe.


An On-Chip Support Vector Machine and Training adjunct were designed. An SVM classifies a given pattern vector X based on training data points into the classes {+1,-1} with maximum margin in feature space [1]. Innerproducts in feature space correspond to a positive-definite kernel K(.,.)  in data space. A nonlinear classifier is thus constructed using a linear classifier in higher dimensional feature space.



Fig 2 : The complete schematic of the circuit.

Padframe Pinout.

VDD and GND : The chip is designed to work of a DC supply of 3V.

DIM0 ... DIM 5 : These input represent the dimensions of the vector input ( 6 dimensions )

CLASSIFY-!TRAIN : When this digital input is Logic 1, the chip will operate to classify the input vector as +1/-1

                                      When this is at Logic 0, the stored vector values will be updated based on the input.

LABEL : In the training mode, this input indicates the classification of the current

OUT-DRAIN-VOLTAGE and OUT-SOURCE-VOLTAGE : D and S voltage inputs for the PMOS transistor which gives the classified output current.

DECAY-LIMIT : This voltage specifies the limit to which a stored margin value must decay before being eligible for replacement.

MULTIPLIER-REF : Reference voltage input for the multiplier. Nominally 1.5V.

OPAMP-BIAS : Bias voltage for the opamps used in the circuit. Nominally 600mV.

V-OPAMP : Reference input voltage for the opamp ( V- ) . Nominally 2.75V .

GLOBAL RESET : On this signal, new inputs are introduced and the flip-flops are reset to Logic 0 output.



Fig 3 : Block Diagram of the circuit.

The circuit takes as input a 6 dimensional vector in the form of voltages from 1 to 2 V DC. The kernel function chosen for implementation was the Gaussian Kernel . The dot product was determined by tying the output lines of the circuit together. This operates on the principle that for exponentials, the product is equal to the exponent of the sum of the indices. Shown below is the circuit schematic as well as the results obtained . As can be seen the current profile is gaussian about the chosen reference of 1.5V. The variation of VOUT produces this current. Different VOUTs are tied together to obtain the dot-product. The output for two stages is shown below.


Fig 4 : Gaussian Circuit and output.

The output voltage(s) of this stage are then the inputs to the multiplier circuit, whose function is to determine the margin of classification ( see first graph ) and based on the value of the label ( +1/-1 ) either source or sink a current on the output node. The various output nodes are tied together to obtain a summation of the current outputs at a node. The schematic and results are shown below :

Fig 5 : Multiplier Circuit and outputs.

The current summed at the node is the margin. Based on whether the chip is in Training mode or Classification mode, the current can be a classified output or can be used to update the values of the stored vector. The circuit to determine which vector to replace is a combination of digital logic and analog circuitry. Based on a reference set off-chip, the first stored value of the margin ( which is stored on a capacitor ) will cause a comparator-FF combination to trigger and switch the current margin into the capacitor. This performs an "update" of the stored value. The FF is reset by a Global Reset signal which signals a new value of the input vector and a fresh cycle of computation. The outputs of the update circuit are shown below :

Fig 6 : Based on a top-down priority ( In 1 > In2 ... ), at any time only one comparator output is high ( 0p1 - Op 4 )

Fig 7 : Loading a new value and Global Reset signal

For the outputs above, CAP-VOLTAGE is an exaggerated decay of a capacitor voltage. When the voltage crosses a particular threshold -1V- in this case , the COMPARATOR-OUT goes high triggering the Latch ( LATCH-OUT ) and a new voltage is stored on the capacitor. The GLOBAL-RESET signal resets the latch and a new cycle of computation continues.


Fig 8 : Complete layout.

Fig 9 : Layout of the Gaussian Circuit.

Fig 10 : Layout of the Multiplier Circuit.

Fig 11 : Layout of the Opamp Circuit.


[1] V. Vapnik, The Nature of Statistical Learning Theory, Springer-Verlag, 1995.


Mihir Naware and Zaki Yahya December 2001.