CMOS Imager for Low-Level Fluorescence Imaging


Josh Cysyk

La Vida Cooper

Weikun Luo




The objective of this project is to design a high quality CMOS imager, especially under low level fluorescence conditions, with potential applications in biological fluorescence spectroscopy, digital photography and other commercial applications.



Modular Specifications and Design


Photo-detector Pixel

Since the pixel was designed for low intensity imaging and the light level is often on the order of 10-100 mlux, which is about the amount of light during a full moon,   a large pixel size is required to capture a sufficient amount of incident photons. There are several methods available to implement a pixel design, such as CCD, Passive Pixel Sensor (PPS), and Active Pixel Sensor (APS).  Although the CCD implementation has some desired advantages, such as very low noise and low dark current, it also has a disadvantage of high power consumption and is hard to integrate with other analog or digital circuits.  Compared with PPS, the characteristics APS has the advantage of low noise, and faster nondestructive reading.  These features correspond well with our design specifications, so photodiode APS implementation was adopted.


In our design, a photodiode is implemented using n+/p-substrate, with an amplifier circuit to provide gain at the pixel level.  Only 4 transistors and 1 capacitor are required at the pixel, maximizing the fill factor of the photosensitive area. With the diode reverse biased, the incident photons generate electron-hole pairs in the depletion region of the diode.  The diode can be modeled as a current source due to the incident light in parallel with a capacitor.  The electrons genenerated are stored on the capacitor.  The cascoded amplifier stage provides the necessary gain for the system. 



APS schematic and layout plots


Pixel Operation descriotion:

At reset, the voltage on the diode is set as the threshold voltage of the inverting amplifier.  As the diode accumulates charge, the voltage decreases linearly as dv/dt = -Iphoto/Cdiode.  If the amplifier has sufficient gain, then the gain of the system is -Cdiode/Cfdbk, and the change in voltage at the output is given as dVo/dt = Iphoto/Cfbck.   The final output voltage will be tint*Iphoto/Cfdbk, where tint is the time allowed for integration. 


 A first order model of the diode capacitance was found to be 500fF.  With a feedback capacitance of 5fF, the gain of the system is 100.   Because the gain is high, a cascoded amplifier stage was required. 


With a 5fF feedback capacitor and an integration time of 1ms, the expected voltage gain of the circuit is 200mV / pA photocurrent.  The full scale range of the ADC is 1V, allowing for 5pA of photocurrent.  An 8-bit ADC is implemented with 1bit resolution of 4mV, corresponding to 20fA of incident light.  Assuming a quantum efficiency of 0.5, at 700nm incident light (typical for fluorescence applications), a 10mlux incident light will generate 30fA of photocurrent, which is 6mV output.  This level of light is just at the limit of resolution of the chip.  More bits in the ADC would allow for finer resolution, however, the noise in the pixel ultimately sets the resolution.  A maximum light level of around 1.5lux will cause the output voltage to saturate at 1V.   The effective range of the chip will be in light levels from 0.01 to 1.5 lux.


Because of the large size of the photodiode, dark current will be a problem.  A first order analysis of the diode region, making liberal assumptions about the depth of the n+ region and the doping profiles, give a dark current level of 400fA.  This is the same amount of current that would be generated from a 100mlux signal.  This dark current cuts into the effective range of light measurements. 



Correlated Double Sampling (CDS) and Analog to Digital Converter (ADC)


A sample and hold circuit is needed to interface with each column of the pixel array.  This circuit was designed using a charge mode approach and allows for parallel reading of the pixel columns, with the rows being read serially.  A correlated double sampling (CDS) circuit is implemented with an inverting amplifier and switched capacitors.  The sampling circuit along with the ADC front end is shown in the following figures.   The hold clock of the sampling circuit is the same as the reset clock for the pixel.  After reset, integration occurs across the feedback capacitor of the pixel.  Towards the end of integration, the voltage value is sampled by the CDS circuit.   At reset, the reset value of the pixel is then sampled.  The output voltage of the CDS circuit is the difference between the final voltage value and the initial reset value; this voltage difference is the photo charge integrated by the pixel. 


The output voltage is then compared to an external ramp signal from 0 to 1V.  A chain of inverting amplifiers with a separate sample and hold clock is implemented as the comparator.  The final output of the chain of amplifiers is a digital signal that goes high when the ramp voltage crosses the sampled pixel voltage.  This digital signal triggers the sampling of the 8-bit counter running concurrently.



CDS and ADC schematic plot


CDS and ADC layout plot




CDS and ADC simulation results


Peripheral Circuits


8 Bit Counter

The eight bit counter outputs the intensity level of a single pixel. The counter was built using eight edge-triggered master-slave D flip flops, thus on the edge of the input clock, the output of each flip flop changes state. The actual output of the counter is acquired by reading the bits in the reverse order that they are flipped, making q0 (1st flip flop output) the least significant bit and q7 (the 8th flip flop output) the most significant bit.  The counter has an enable and reset for testing and operation.



 8 Bit Counter schematic plot


8 Bit Counter layout plot


4 bit counter

The four bit counter interfaces with the input bits A0-A4 of the row select circuit to trigger the readout of each row of the pixel array.  The counter was built with 4 edge-triggered master-slave D flip flops, thus on the edge of the clock the output of each flip flop changes state. The actual output of the counter is acquired by reading the bits in the reverse order that they are flipped, making q0 (1st flipflop output) the least significant bit and q3 (the 4th flip flop output) the most significant bit.  An enable and reset have been added for testing and operation.


4 Bit Counter schematic plot


4 Bit Counter layout plot



4 Bit Counter simulation results



 Row selector

The row select circuit sequentially chooses each row of the pixel array for intensity readout, by receiving a four bit number from the four bit counter which causes the “select_not” signal for that particular row to go low.




Row selector schematic and layout plots


Row selector simulation results




D flipflop (storage cell)

The  edge triggered D nand flip flop  receives an input D and on the clock edge outputs a state Q which takes on the state of the input.  This cell is used in a 8x16 array to receive the intensity level of a single pixel (8bit counter output for a row of 16 pixels).



 D Flip-flop schematic plot



D flip-flop layout plot


D flip-flop simulation results


Parallel to serial converter


The eight bit parallel to serial converter receives 8 parallel bits form an 8 bit column of the D flip flop array and shifts this number out serially to a pin.  This register is composed of 8 master slave D flip flops that each receive the output of a two input multiplexer.  The two input multiplexer receives a parallel input bit and the output bit from the preceding D flip flop. The state of the mode control bit determines if the multiplexer outputs the incoming parallel bit or the shifted bit from the previous stage.  The parallel to serial register has an enable, reset and mode control bit for testing and operation.



Parallel to serial converter schematic plot


One bit cell schematic plot


Parallel to serial converter layout plot


Parallel to serial converter simulation results


Master/Top level Design




Top level schematic and layout design




Top level clock plot


Clock Plot Explanation

S (1st clock signal )

Sample phase for the CDS circuit

H(2nd clock signal)

Hold phase for the CDS circuit and Reset signal for pixel

H’(3rd clock signal)

Hold phase for the ADC circuit, during which time the output from the CDS  is compared to external signal Vramp

S’(4th clock signal)

Sample phase for ADC circuit

Dout (5th signal)

Output signal from the ADC, paired with H’ triggers the sampling of the 8bit counter for an intensity reading

4-bit(6th clock signal)

Clock input for the 4bit counter interface of row selector circuit

8-bit(7th clock signal)

Clock input for the 8bit counter

Note: All signals are external input signals with the exception of Dout.




Pin list table

Pin Number

Pin Name




Bias voltage for the cascoded amplifier stage in the pixel



Bias voltage for nmos cascode in inverterting amps  used in CDS and ADC



Bias voltage for inverterting amplifier used in CDS and ADC



Bias voltage for pmos cascode in inverterting amps  used in CDS and ADC






Sample clock  in ADC



Hold clock in ADC



Sample clock in CDS



Hold clock in CDS



Bias current for pixel amplifier stage



Global reset signal for pixel rows



Enable signal for 4 bit counter used for row selection



Reset signal for 4 bit counter used for row selection



Clock for 4 bit counter used for row selection






Digital output Column 2



Digital output Column 0



Digital output Column 10



Digital output Column 5



Digital output Column 8



Digital output Column 1



Digital output Column 11



Digital output Column 6



Digital output Column 9



Digital output Column 4



Digital output Column 3



Digital output Column 7



Enable signal for 8 bit counter for ADC



Reset signal for 8 bit counter for ADC



Clock for 8 bit counter for ADC



Digital output Column 13



Digital output Column 12



No connection



Reset for Parallel to Serial Converter



Control for Parallel to Serial Converter



Enable for Parallel to Serial Converter



Clock for Parallel to Serial Converter



Digital output Column 16



Digital output Column 15



Voltage Ramp signal for ADC



Future Work

 This chip will be fabricated in January of 2004. Thus in an effort to optimize our design and reduce the overall area of the layout alternative configurations will be explored which include (but not limited to) the utilization of an 8 to 1 multiplexer  to interface with each column of the 8x16 D flip flop array of intensity outputs.  Simulations will be performed to evaluate the tradeoff of area vs performance, in addition to optimization in order to finalize the design. 




Dr. Gert Cauwenberghs

Shantanu Chakrabartty

Swati Metha



J. Rabaey, A. Chandrakasan,B. Nikolic,  Digital Integrated Circuits, 2nd Edition, Prentice Hall, NJ, 2003