520.490 Analog and Digital VLSI Systems

The SIC Chip

Harvesting Power for Implanted Devices

 

David Ploskonka

dplosko1@jhem.jhu.edu

 

Christian Sauer

csauer@jhu.edu

 

 

The SIC Chip (top level layout with padframe)

 

Objectives

The SIC (Sensor Interface Conditioning) chip provides the necessary link between implanted devices and the outside world.  The chip harvests power from a 4 MHz radio frequency signal to provide a constant DC voltage for any sensor it is paired with.  The chip also supplies a clock signal for the sensor, currently 1 or 4 MHz, although these frequencies can be easily adjusted.  To totally eliminate the need for any hardwired connections, the chip also takes in a digital stream of data from the sensor, encodes the data stream, and wirelessly transmits the encoded data back to the base station.  No specific sensor is currently paired with the chip; however, its design allows for easy integration with a number of different sensors.

 

Specifications

The chip receives a differential voltage signal from off-chip – simulated with a sinusoidal voltage source in Cadence, but captured from the environment by an off-chip inductor and capacitor in the real world.  This signal can range in amplitude from 8 to 12 Volts (after fabrication, a Zener Diode will be used on this input to ensure that the signal does not endanger the chip).  The resulting differential waveform contains much power, but in an unusable form.  To render it more useable, the signal is passed through a rectifier and low pass filter.  The rectified signal is approximately 5 Volts but is quite unstable.  Any attempt to draw current from it will result in a dramatic drop in voltage.  A regulator is used to lower and maintain the Vdd voltage at 3.3 Volts regardless of the load on the circuit.  The maximum current that can be obtained is approximately 1mA (corresponding to a 3 kOhm load).  As with most regulators, this implementation requires a steady voltage reference.  In our circuit a Masterbias1 voltage bias generator supplies a reference voltage of 830 mV.  In our design we found that the digital logic on the chip (for encoding and other operations) adds noise, on the order of 100 mV, to the regulated voltage.  In order to supply a clean Vdd to the sensor we use a second voltage reference, isolated from the digital logic on the chip.  The two supplies form the Vddd (digital supply) and Vdda (analog supply) outputs of the chip. 

 

Besides supplying these voltages to the sensor, the SIC chip also performs several digital operations.  From the initial 4 MHz waveform, a 4 MHz clock is recovered.  The 4 MHz clock is then down-clocked to 1 MHz for output to the associated sensor.  The chip is also able to accept a data stream from the sensor.  This NRZ (non-return to zero) data stream is encoded by a modified Miller encoding scheme; each logical “1” in the data stream is represented by a pulse of a width determined by the frequency of the pulse clock.  The pulse clock input can be provided from the 4 MHz clock or the 1 MHz clock generated by the chip itself, or it can be supplied by the sensor with which it interfaces. The encoded signal is applied to a switch that modulates the impedance of the antenna coil, causing detectable changes in the base station that can be observed and recorded to recover the data stream.

The SIC Chip (top level schematic)

 

 

Pin list for the SIC Chip

1

Vddd – digital supply voltage

40

 

2

Data_In – input data stream

39

Vdda – analog supply voltage

3

Pulse_Clk – clock for transmission

38

 

4

Data_Clk – clock controlling data rate

37

 

5

 

36

Gnd

6

Clk_1M – 1 MHz clock out

35

 

7

Clk_4M – 4 MHz clock out

34

 

8

 

33

 

9

 

32

 

10

Gnd

31

 

11

Data_Out – encoded data

30

 

12

 

29

Vrect – raw rectified voltage

13

 

28

Vref – reference voltage

14

 

27

 

15

 

26

 

16

 

25

 

17

Ant1 – input from antenna

24

Ant2 – input from antenna

18

 

23

 

19

 

22

 

20

 

21

 

(inputs in blue, outputs in red)

 

Results

 

In response to an 8 V amplitude sine wave (not shown in the above graph), the rectifier outputs a 5 V signal (the top waveform, Vrect), which is turned into a steady 3.3 V signal by the regulator (the middle waveforms, Vdda and Vddd).  The voltage reference maintains a constant 830 mV signal (the bottom waveform, Vref).

 

In the close-up view of the preceding graph, the difference in noise in the Vddd and Vdda signals is apparent.  The noise in the Vddd signal is approximately 100 mV (note the jagged waveform just above 3.0 V), while the noise in the Vdda signal is approximately 5 mV (note the relatively smooth line passing through the jagged waveform).  This graph illustrates the need for separate power supplies for digital and analog circuitry.

 

 

Clock signals of 4 MHz (middle waveform) and 1 MHz (bottom waveform) are generated from the antenna signal (top waveform).  The digital logic on the chip introduces noise into the clock signals, but the noise is on the order of 100 mV, below the tolerances required for digital operations.

 

 

The NRZ data stream to the chip (second waveform from the top), sent at the rate of the data clock (top waveform), is encoded by a modified Miller coding scheme.  For each logical “1” in the data stream, a corresponding output pulse is generated (bottom waveform). The width of the output data pulse can be modified by changing the frequency of the pulse clock (second waveform from the bottom).

Schematics

To see more detailed schematics of the individual components on the chip, click here.

References

1. Delbruck, Tobi, “Bias Current Generators,” Telluride Neuromorphic Engineering Workshops, 2000

2. Finkenzeller, Klaus, “RFID Handbook,” Chichester, New York, John Wiley, 1999

3. Ghovanloo, Maysam and Najafi, Khalil, “Fully Integrated Power Suppy Design for Wireless Biomedical Implants,” 2nd Annual International IEEE-EMBS Special Topic Conference on Microtechnologies in Medicine and Biology, May 2002

4. Panitantum, Napong et al, “A CMOS RFID transponder”, in press