520.492 Mixed Signal VLSI Systems

MultiChannel EEG Recording System

Mohsen Mollazadeh


Continuous monitoring of brain activity is essential in understanding neural substrates of many physiological and pathological brain functioning. Low amplitude of EEG signals as well as their noisy nature make it hard to detect them (1-500 uV and .1-500Hz). Another issue is the DC offset of the signal due to electrode-tissue interface. This DC offset is usually 20-50 mV and 1000 times bigger than the signal. Thus, a very low a noise instrumentation amplifier is required to amplify these signals and remove the DC offset. Typically, electrodes are placed on the scalp of patients and a large number of wires connect to a huge rack of instrumentation amplifiers connected to a computer. This makes the patient very uncomfortable. Also, the advent of fully implantable microelectrode arrays has created the need for integrated micropower amplifiers. 

Several chips for EEG or neural recording have been reported in the literature [1]-[5]. [1] introduces a circuit that has a 7.8 uVrms input referred noise, which is above the signal amplitude. Noise issues are solved in [2] at the expense of relatively large silicon area, 2.2 mm by 2.2 mm. [3] and [4] don't mention noise figures, and [5] uses a BiCMOS process to obtain a low noise amplifier. Off-chip capacitors are used in some of the designs [6] to reduce noise but they are less suitable for implantable microsystems.  

Here, we design an EEG recording system that amplifies the signal and produces a digital output that can be connected to a RF chip, so that data can be sent wirelessly to a base station. The system has four channels so that four EEG data streams can be recorded simultaneously. The amplifier has a gain of 100 db and input referred noise of 4.4 uVrms, while consuming 72 uW of power form a 3.3 V power supply. It has a tunable bandwidth so that one can record any signal of interest (alpha, beta, ...). The output of the amplifier is then connected to a delta-sigma A/D converter that has a controllable gain and resolution (Max. Resolution: 10 bits, Max. Gain: 1024). Minimum LSB achievable with this configuration is 4 uV, matching the noise level of the amplifier. Sampling frequency is dependent on gain and resolution of the system.  

System Design


As stated above, amplifiers used for biosignal recording should have a low noise input referred noise and good DC rejection. Low noise figures can be achieved either by having wide input PMOS and large load transistors or using chopper modulated technique. The former is a well understood method that is first described by [7]. In chopper-modulation techniques the signal is first shifted to frequencies above 1/f noise and then amplified. Low noise instrumentation amplifiers  have been achieved in this way [8],[9] but we avoid this method due to it's complexities.  Here we used a novel technique to over come noise. OpAmp designed is a two stage voltage amplifier (Fig. 1). Noise analysis of the circuit reveals the input-referred noise to be

where gm0, gm8, gm13 and gm15 are transconductances of input PMOSes, first stage load, second stage input and second stage load transistors respectively. thus for having low noise, input PMOS should be wide and input loads should be large. The second stage transistors don't have much effect on the noise since their noise contribution is divided by the gain of first stage. 


Fig.1 : Schematic of voltage amplifier used in instrumentation amplifier 

Sizing of the first stage was done to get a good noise performance. Ibias is 8 uA and the bias current for the second stage transistors was set to 1 uA by "vbias" and "vbiasc. Aslo this voltage controls bandwidth of the amplifier. Capacitors were added between first and second stage to limit bandwidth of OpAmp. Clamp transistors M35 and M36 in the first stage are used to minimize transient voltages during  slew-rate limiting. Also they would help to get lower common mode gain and also improve noise performance. A simple bias circuitry is used to generate gate voltages of these transistors (Fig. 2). One advantage of this circuit is that any change id voltage of "isrc" node will be reflected in "vbiasf" node and this will tune clamp transistors so that they would never be on in the normal operation range of the OPAmp.   

Fig. 2: Bias Circuit For Clamp Transistors

Also, a common CMFB circuitry is added to the second stage to determine output common mode voltage (Fig. 3).

Fig. 3: Common Mode Feedback Circuit

 The OpAmp was then used in a fully differential configuration with capacitively-coupled inputs (Fig. 4). DC rejection is achieved by generating high resistances in parallel to the capacitor in the feedback loop.


Fig.4: EEG Amplifier

Fig. 5 shows a novel method was used to generate high resistances. Analyzing this circuit, you can find out that conductances of M5 and M6 transistors equal to I/Vth where I is the current passing through the transistors and Vth is the thermal voltage. By having the same transistors in the feedback loop and having the same gate to source voltage, one can achieve high resistance up to Teraohms in the feedback loop (sources of the transistors are connected the the common mode voltage).  


Fig. 5: High resistance generator circuitry


Simulation Results

Figure 6 shows the result of Transient and AC simulation


Figure 7 shows the simulated amplifier input referred voltage noise spectrum. the amplifier has a corner frequency around 100 Hz and thermal noise level of 28.5 nV/sqrt(Hz)


Fig. 7: Input referred voltage noise spectrum 

Integration of area the  curve from .5 Hz to 50 Khz shows a rms noise voltage of 4.5 uVrms.



Parameter Simulation
Supply Voltage 3.3 V
Supply Current 8 uA
Gain  40 db
Bandwidth 10 KHz
Low frequency cutoff .5 Hz
Input Referred Noise 4.5 uVrms
Total Power Consumption 72 uW


Delta-Sigma Analog to Digital Converter

The circuit used here is mainly the same circuit as in [10] and additional information can be found there. Just an OTA is used to convert the output voltage of the amplifier to current and then this current is sampled by delta-sigma. Figure 8 shows the schematic of the circuit.

Fig. 8: schematic of Delta-Sigma Modulator

Simulation Results

Figure 9 shows the integrated output and output bit of delta-sigma for a constant input current

Fig. 9: output bit of delta sigma and integrated output

Digital Building Blocks

Digital Parts used in Analog to digital Converter or clock generation are custom circuits. schematics of them can be found here.


System Integration

The chip contains four channels, each channel with EEG amplifier, delta-sigma modulator, and decimator. A boundary scanning shift register outputs the digital output of the four channels in bit-serial format. The bit-serial format is intended to interface the chip directly with a telemetry chip (see 520.490, Fall 2003 projects).

Fig. 10: Schematic of the chip


Fig. 11: Schematic of one channel

The layout is performed in a AMIS 0.5 um process. Figure 12 shows a partial layout of the chip.

Fig. 12: Layout of four EEG channels


Pin List for the ERS Chip 


Vddd-digital supply voltage


Int_out-integrated output of delta sigma of last channel


SysClc-Chip master clock


Serial_out-serial output of the chip


Convert-Conversion signal


Ampoutp-positive output of the OpAmp of last channel


Convertn- inverted of Convert


Ampoutm-negative output of the OpAmp of last channel


ReadoutClk-read out clock




Datain-gain and resolution data line




Clkshiftinds-clock for gain




Clkshiftinres-clock for resolution






Vref-reference voltage for delta sigma 




vmid-comparison voltage for delta sigma


Vtunehigh- voltage for tuning the cutoff frequency of high pass filter


Vinplus1- Channel one input


Vbiascmfb- common mode voltage


Vinminus1-Channle one input


Vbias-bias voltage of second stage of amplifier


Vinplus2- Channel two input


Vbiasc-bias voltage for cascode of "vbias"


Vinminus2-Channle two input


Ibias-bias current for OpAmp


Vinplus3- Channel two input


IOTA-bias current of OTA


Vinminus3-Channel three input


Iref-Reference current


Vinplus4- Channel four input


Vbiasp-bias voltage for PMOS bias in cascoded inverter


Vinminus4-Channle four input


Vcasp-bias voltage for cascoded PMOS in inverter


Vdda-Analog supply voltage


Vcasn-bias voltage for cascoded NMOS in inverter



*. inputs in black, outputs in red


Dr. Gert Cauwenberghs
Milutin Stanacevic
Kartik Murari
Christian Sauer


[1] P. Mohseni, K. Najafi, S. Eliades and X. Wang, " Wireless multichannle biopotential recording using an integrated FM telemetry circuit" Neural Syst. Rehab. Eng. IEEE Trans., June 2005. 

[2] R. R. Harrsion and C. Charles, " A low-power low noise CMOS amplifier for neural recording applications" IEEE J. Solid-state Circuits, vol. 38, no. 6, June 2003.

[3] R. H. Olsson III, M. N. Gulari and K. D. Wise, " Silicon neural recording arrays with on-chip electronis for in-vivo data acquisition" IEEE-EMBC Conf., May 2002.

[4] P. Irazoqui-Pastor, I. Mody and J. W. Judy, "In-vivo EEG recording using a wireless implantable neural transceiver" IEEE-EMBC Conf., March 2003.

[5] R. Rieger, J. Traylor, A. Demosthenous, N. Donaldson and P. Langlois, " Design of a low-noise preamplifier for nerve cuff electrode recording" IEEE J. of Solid-state Circuits, vol. 38, no. 8, Aug. 2003.

[6] J. Ji and K.D. Wise, "An implantable CMOS Circuit interfacefor multiplexed microelectrode recording arrays" IEEE J. Solid-State Circuits, vol. 27, pp.433-443, Mar. 1992.

[7] J. Bertails, "Low-frequency considerations for MOS amplifier design" IEEE J. Solid-State Circuirs, vol.sc 14, no. 4, Aug 1979.

[8] C. Menolfi and Q. Huang, " A fully integrated, untrimmed CMOS instrumention amplifier with submicrovolt offset" IEEE J. Solid-State Circuits, vol. 34, no. 3, Mar 1999.

[9] M. Dagtekin, W. Lui and R. Bashirullah, " A multichannel chopper modulated neural recording system" IEEE EMBC Conf., Oct. 2001, Turkey.

[10] K. Murari, N. Thakor, M. Stanacevic and G. Cauwenberghs, "Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing", IEEE EMBC , vol. 6, pp. 4063 -4066, Sep. 2004.

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