520.492 Mixed-Signal VLSI Systems

An Adaptive LMS Filter System for Noise-Canceling Microphones

Mike Chi, Beatriz Olleta, Katherine Tsai

ychi2@jhu.edu, b.olleta@ieee.org, kattsai@jhu.edu

 

Chip Layout – Top View (4 x 4 tiny chips)

 

Objectives

A VLSI implementation of the adaptive LMS algorithm was built for a noise canceling system with two microphones. One microphone is placed near a source of acoustic noise, while the other is used to pick up a signal contaminated with a correlated version of the noise source. The on chip adaptive filter operates in the frequency domain and outputs a clean signal.

 

 

Specifications

Figure 1: Adaptive Filter System [1]

 

A block diagram of the adaptive filter system is shown in Figure 1.  The adaptive filter contains 16 taps in the frequency domain.  The taps span the human speech range from 100 Hz – 8 kHz and are used to modify the noisy signal based on a calculated coefficient.  The coefficient weights are updated using the sign-sign LMS (SS-LMS) algorithm based on the error difference between the primary input signal and the output of the adaptive filter.  The adaptive filter should converge to match the noise source such that the output of the system is the desired signal.

 

Matlab Simulation:

 

The system was modeled using matlab and a sample sound file to test the effectiveness of the LMS filter.

 

Original Sound File

 

 

Contaminated with White Noise

 

 

Post Filtering

 

 

The output sound files were analyzed with Adobe Audition. The above pictures show the spectral view of each file (energy plot of frequency versus time).

 

Circuits and Results

 

Preamplifier [2]:

 

Figure 2 shows the schematic of the preamplifer used to amplify the microphone signals.  It was designed to provide a gain of 1000 to interface the weak (uV – mV range) microphone outputs with the filter bank.

 

Figure 2. Preamplifier

 

Figure 3 shows the operational transconductance amplifier (OTA) used in the preamp. 

 

Figure 3. Operational transconductance amplifier

 

Figure 4 shows the common-mode feedback (CMFB) circuit used in conjunction with the OTA.

 

Figure 4. Common-mode feedback circuit

 

Simulation results (Figure 5) show that the preamplifier has a differential gain of 60 dB with a low-end cutoff of 103 Hz and a high-end cutoff of 44 kHz.   The total input-referred noise level is 5.087 uV from 100 Hz to 10 kHz. 

 

Figure 5.  Preamplifier gain-bandwidth simulation results

 

The layout of the preamplifier is shown in Figure 6.

 

 

Figure 6. Preamplifier layout

 

 

Multiplying DAC [3]:

 

The 8-bit DAC is used to multiply each frequency band with its associated coefficient. It is implemented via an array of switched capacitors controlled by counter that can both increment and decrement.

 


The capacitor array is essentially two variable capacitors that divide the differential input based on the size ratios of the two capacitors.

 

 

 


The value of C is directly proportional to the output of the counter, thus the output voltage is just the count multiplied by the difference of the input voltage. The counter itself is synchronous, made of full adders and latches with increment/decrement controlled by a comparator which calculates the error sign (implementing the SS-LMS algorithm).

 

Figure 7. Capacitor array

 

Thermometer coding is used to size the capacitor sizes to facilitate better matching in layout.

 

 

Figure 8.  Layout showing one DAC

 

 

Figure 9.  Analog simulation of DAC

 

Simulation results showing the DAC incrementing from 0 to 255 and decrementing back to 0. It includes overflow protection logic. The two input signals to are at 2.5V and 2.8V, and switched midway to control the switch the counter from increment to decrement.

 

 

Filter Bank:

 

The filter decomposes the noise signal into 16 different frequency bands from 150 Hz up to 8 kHz.  The gm-C filter is ideal since is tunable after fabrication.  In addition, only one design is needed to implement all sixteen bands.  The main component in this filter is the transconductor.  The following circuit is used because it offers a high degree of linearity.  With this configuration, very small gm values can be obtained, which are necessary to generate the lower bandpass frequencies without having to increase the sizes of capacitors.

 

Figure 10. Transconductor stage schematic

 

The gm stage has a linear response from 0 to 3.3 V as shown Figure 11.

 

Figure 11. Transconductor DC response

 

The biquad configuration [4] used to implement a 2nd order filter is shown in Figure 12.

 

Figure 12. Biquad bandpass gm-C filter

 

To obtain the desired 4th order filter, two of the 2nd order filters are cascaded. The filter bank was divided in two main blocks - the first eight filters cover the low frequencies while the other eight cover the high frequencies. The high frequency filters use the same gm-stages but have smaller capacitors (80fF and 320fF).  Each filter is biased using a current that is then mirrored into the corresponding gm stages. Figure 13 shows the filter bank, while Figures 14 and 15 show AC and transient responses, respectively.  The transient response, shown for a single filter, illustrates that the filter has a linear response and does not add distortion, while the AC response shows that the bandpass frequencies are equally spaced.  It should be pointed out that these frequency values are easily tuned by the bias currents.

 

Figure 13. Filter bank

 

Figure 14.  Filter bank AC response

 

Figure 15. Single filter transient response

 

Figure 16 shows a complete fourth-order filter layout. It can be seen that the gm stages, especially the resistors and the big NMOS transistors operating in subthreshold, take up most of the area.

 

Figure 16. Layout of a fourth-order filter

 

Pin Diagram of the Chip:

 

1

Ib1 – High res. circuit bias (500 nA)

40

Test

2

Ib2 – High res. circuit bias (-500 nA)

39

Test

3

Vb1 – CMFB bias (1.875 V)

38

Test

4

Ib3 – OTA bias (4 uA)

37

Test

5

Ib4 – PMOS cascode  bias (1 uA)

36

Test

6

Ib5 – NMOS cascode bias (-1 uA)

35

Test

7

Vb2 – High res. circuit bias (2.5 V) 

34

Test

8

Vin – Microphone input

33

Test

9

Ib6 – Comparator bias (60 uA)

32

Clk

10

Vb3 – Transconductor bias (1.5 V)

31

Gnd

11

Vb4 – Transconductor bias (3.5 V)

30

Vdd

12

Ib7 – Tranconductor bias (4 uA)

29

Ib24 – Filter bias

13

Ib8 – Tranconductor bias (2 uA)

28

Ib23 – Filter bias

14

Ib9 – Filter bias

27

Ib22 – Filter bias

15

Ib10 – Filter bias

26

Ib21 – Filter bias

16

Ib11 – Filter bias

25

Ib20 – Filter bias

17

Ib12 – Filter bias

24

Ib19 – Filter bias

18

Ib13 – Filter bias

23

Ib18 – Filter bias

19

Ib14 – Filter bias

22

Ib17 – Filter bias

20

Ib15 – Filter bias

21

Ib16 – Filter bias

 

 

References

[1] Widrow, B. et al., “Adaptive noise cancelling: principles and applications”, Proceedings of the IEEE, Dec. 1975, pp. 1692 – 1716.
[2] Harrison, R.R. et al.,  “A ow-power low-noise CMOS amplifier for neural recording applications”, IEEE Journal of Solid-State Circuits, Vol. 38, Issue 6, June 2003, pp. 958 – 965.

[3] Stanacevic, M., G. Cauwenberghs, “Micropower gradient flow acoustic localizer”, submitted for publication in 2005.

[4] Johns, D. A., K. Martin, Analog Integrated Circuit Design, John Wiley and Sons, Inc., 1997, pp 582 - 584.