Homework Assignments
Spring 2005
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Homework 1: due 2/21/2005. Schematic capture, layout and LVS (Cadence).
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Homework 2: due 2/28/2005. Circuit analysis and synthesis (paper and pencil). Solutions
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Homework 3: due 3/7/2005. Circuit design and simulation (Cadence).
Gert
Cauwenberghs