520.496-497 VLSI Design and Prototyping Workshop
Hands-on laboratory where students individually complete the
design, layout, and testing of a VLSI circuit implementing a
system-on-chip. Examples include CMOS computational imagers, video
and speech coders, pattern recognition processors, and
biointerfaces. Both semesters need to be completed in order to receive
course credit. Chips are fabricated through MOSIS at the end of the first
semester, and experimentally characterized in the second. Coursework
includes in-class presentation of design and measured results.
Instructor: Prof. Gert
Cauwenberghs, Barton 209/400B,
gert@jhu.edu
Time and location: Th 1-2, Barton 225, plus regular individual meetings
Read the Ethics Statement
Credits: 3
Pre/Coreqs: 520.491, 520.492, or 520.493
Schedule
Fall 2004 (520.496):
- Week 1 (9/9): introduction and example projects
- Week 2 (9/16): project definition and outline
- Week 3 (9/23): system-level design and optimization
- Week 4 (9/30): schematic design -- cell level
- Week 5 (10/7): cell-level simulations
- Week 6 (10/14): schematic design -- chip level
- Week 7 (10/21): schematic design -- interface level
- Week 8 (10/28): chip/interface-level simulations
- Week 9 (11/4): layout -- floorplanning
- Week 10 (11/11): layout -- cell level
- Week 11 (11/18): LVS verification and post-layout simulations
- Week 12 (12/2-3): Final presentations
Spring 2005 (520.497):
- Week 1 (2/10): introduction
- Week 2 (2/17): experiment definition and design
- Week 3 (2/24): board-level design
- Week 4 (3/3): software (Verilog/VHDL) co-design
- Week 5 (3/10): system-level simulation
- Week 6 (3/24): PCB layout
- Week 7 (3/31): PCB prototyping and functional verification
- Week 8 (4/7): preparation of experiments
- Week 9 (4/14): testing -- circuit characterization
- Week 10 (4/21): testing -- system characterization
- Week 11 (4/28): application-level experiments
- Week 12 (5/5-6): Final presentations
Gert Cauwenberghs
September 8, 2004