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Getting Started
Examples
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Bluesky
About
Getting Started
Examples
Publications
Hardware Docs
GitHub
Bluesky
Section Navigation
Hardware Guide Book
0 Introduction
Our hs_api Example
Basic Hardware Architecture Map - Low-Level Physical Organization
Hardware Component Definitions (Low-Level)
hs_bridge Role and Responsibilities
1 Initializing the Network
1.1 How the Network Looks in Hardware
1.2 How the Network is Written to the FPGA
Diagram of CRI Stack During Network Compilation
2 The Network Comes to Life
2.1 Visualizing the Network’s Signal Processing in Hardware
2.2 State Machine Coordination and Control Signals
2.3 The Code Behind Execution
Diagram of FPGA During 1 Timestep
3 Verilog Files Review
command_interpreter.v
External Events Processor Module Family
hbm_processor.v
input_data_handler.v
internal_events_processor.v
pcie2fifos.v
Pointer FIFO Controller Module
Spike FIFO Controller Module
4 Implementing RSTDP
4.1 What is R-STDP?
4.2 Reading and Writing Synapses
4.3 Hardware Implementation of R-STDP
Supplementary Information
Appendix: Hardware Glossary for Software Experts
Packet Encoding Reference
Address Encoding Explained
PCIe and HBM Packet Definitions
PCIe and HBM Packet Definitions
HiAER Spike Hardware Docs
4 Implementing RSTDP
4 Implementing RSTDP
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