HiAER Spike Hardware Docs#

Warning

Under Construction — This documentation is a work in progress and may be incomplete or subject to change.

Welcome 👋

This documentation teaches hs_api experts and computational neuroscientists how the hardware behind hs_api works. HiAER Spike is built on FPGA technology, which is programmable via hardware language (SystemVerilog) and communicates with the host system (CPU) via hs_bridge. Rather than walking through each file, this documentation teaches from the top down:

Introduction shows a basic hs_api Python implementation for a tiny, 2 layer network.#

We will learn everything in the context of this network so that each component is grounded in an example.

  • The Python file defines and compiles the network and runs 10 timesteps of inputs on the network

  • Has a page introducing all our hardware components, how they’re connected, units of communication, capabilities

  • Has a map visualizing the hardware components and connections

Chapter 1 shows you how the network looks in hardware.#

1.1 Explains the locations of everything conceptually, including a visualization
1.2 Explains how the network is written into the FPGA from the host using hs_bridge and SystemVerilog code

Chapter 2 shows how the hardware processes a timestep of the network in multiple phases#

2.1 Walks through the phases of a timestep conceptually, no code. Introduces FPGA/Verilog modules as black boxes.
2.2 Walks through phases of a timestep in SystemVerilog code; beginning to explain the FPGA/SystemVerilog modules.
2.3 Introduces the concept and implementation of the hardware’s state machine.

Chapter 3 further explains the hardware design#

Each page of Chapter 3 is dedicated to a SystemVerilog file. The first half of the page is essentially a README for the file, followed by the SystemVerilog file itself (heavily commented)

Chapter 4 shows how to implement R-STDP on HiAER-Spike#

R-STDP is a form of biologically inspired supervised weight update rule (What is RSTDP?). To implement it, we need to know …

  • how to update weights:

  • how to implement coincidence STDP:

    • (not yet written)

  • how to implement the eligibility trace:

    • (not yet written)

Supplementary Information#

Includes:

  • Appendix: a long list of key terms throughout the whole documentation, thoroughly explained for hardware beginners

  • Packet Encoding Explained: an explanation of how PCIe TLP packets work for Host-to-FPGA and FPGA-to-Host communication

  • Addresses Explained: an explanation of how addresses are encoded/

  • Bit Encoding = explanation of how information is standardly encoded for hardware in hex code