FINAL DESIGN AND LAYOUT PROJECT
Spring Semester 2005
A. Group Composition and Project Definition
Organize yourselves in groups of 1-4 persons, 2 or 3 being optimal. Define a project. Look through examples from previous years, and if you are short of inspiration you will be given a project.
B. Project Schedule:
System Outline: by 3/10
Circuit cells and simulations: by 3/24
Complete schematic: by 3/31
Cell layout: by 4/14
Complete layout within TinyTM pad frame: by 4/21
Verification: by 4/28
Final report: by 5/5
Final project presentations 5/5 – 5/6
Final "product" (Cadence, schematic and layout) 50 %
System design, circuit schematic, LVS (*) 40 %
Final report (1 page + diagrams) and presentation (10 min.) 10 %
(*) Keep a (notebook) record of all work performed during the project, according to the above schedule (system outline, circuits, simulations, ...). The notebook records will come handy in preparing and documenting the final project report.
1. System Outline
Define the block diagram of the system you want to implement, with the functional description of the major parts (e.g.: integrator, multiplier,...). The description should be fully quantitative with clear specification of where signals flow (What is input and output, and interfacing of parts?) and how data is handled (analog, digital, continuous-time, discrete). Find values or ranges of operational values for any parameters governing the system (e.g. coefficients of filters), and analyze the operation at the system level (What are the output waveforms and intermediate waveforms for given input waveforms?). When in doubt or certain parts are not clearly defined or optimized at the system level, do some necessary simulations (at the block-diagram level).
Notebook record: system block diagram, with quantitative description of operation including I/O and interfacing waveforms (obtained from simulations, if necessary).
2. Cell Circuit Design
Come up with (elegant) circuits implementing parts of the system (e.g. amplifiers, integrators, modulators, ...). Retain the hierarchy and organizational structure of the block diagram level design. Make sure signals interface properly (in format, impedance, and in timing) between different circuit cells, according to the arrangement of the blocks. Define all bias levels (or how they are constructed from other supplied bias levels through additional bias circuitry) and voltage or current waveforms used in the timing and control of the circuits. Simulate the design.
Notebook record: print and annotate the circuit diagrams of all cells used to represent the functional blocks in your system, retaining the hierarchical structure. Define bias levels and signal and control waveforms, and include printouts of simulations.
3. Full Schematic Design
Arrange instances of the cells combining to construct the overall system and implement all its functions. Pay much attention to the detail of correctly interfacing the circuit blocks, and make sure the design reflects the hierarchical and modular structure of the system-level block diagram. Typically, the amount of circuitry needed to interface all blocks together should be much smaller than the actual circuitry contained within the circuit blocks themselves.
Notebook record: Same as the cell-level design, but now at the top-level of the hierarchy.
4. Layout of the Cells
Layout the cells in Cadence using Analog Artist.
Make sure the cells abut properly when later combined together (e.g. as instances in an array). There should be a sufficient number of Vdd and GND connections to well and substrate (one bulk contact per 5 transistors connecting to that bulk). Lines should be sized according to the amount of current they need to accommodate. While gate voltage bias lines can be poly, lines that carry current or that need to respond fast to voltage changes should be metal1 or metal2. For large scale signal interconnect on a 2-D grid, use metal1 horizontally and metal2 vertically (or vice versa) and make sure to be consistent in order to avoid cross-over Via (metal1 to metal2) bridges.
Note: Label the I/O interfaces and signal/power lines of all cells with meaningful names (GND, Vdd, CARRY, Vin, Iout,...) which conform with the schematic.
5. Complete Layout Including Pads
Combine the cells in the layout to implement the complete schematics as previously defined, and add the interfacing circuitry at appropriate levels in the hierarchy of cells. Retain the structure of the schematics, with coinciding names for the cells in the layout and the subcircuits in the schematic. Make sure to interconnect power and signal lines correctly, with power lines (GND, Vdd, ...) having a large width.
Include the total layout in a pad frame (provided) and route the external pin connections. Keep in mind the useful area that you can fill up with your circuits to fit within the padframe.
Electronic record: send a pointer to your Cadence library. Make sure to use a library name that is representative of your project.
6. Layout Verification
Run LVS on the complete layout and schematics files, and correct the layout vs. the schematics until both converge. Also, run a complete DRC on the layout file. To your advantage, you should start running LVS and DRC on the cells in the earliest stages of the layout. The final LVS check also marks the end of the project (one week after presentations). You have the chance to make changes according to discussions in class, etc.
7. Project Report and Presentation
Every project group will generate a final report (about 1 page/person, plus schematic diagrams and pin connections) in electronic format, describing the chip. It should be clear from the report what the chip is supposed to do, and who did exactly what in the project. The report should be to the point, with as little general background formulation and as much chip specifics as possible. Attach copies of (relevant sections of) the notebook records to the printed version of the report. Besides the report, every group should prepare a presentation in class (see schedule) with basically the same content (at most 5 min./person, plus open discussions). The report is due the week after the presentations.
Electronic format: The report needs to be submitted in HTML format, and need to include all graphics and other referenced documents. All class reports will be posted on the web, accessible from the class web page. An example report in HTML format is posted here.
8. MOSIS Fabrication
You can have your group's design fabricated through MOSIS in 0.5µm CMOS technology, provided that you commit to thoroughly testing the fabricated chips after they come back from MOSIS. Test facilities are available in the Adaptive Microsystems Laboratory. You will also have plenty of chance to modify the layout before we send it off for fabrication.