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Detector Array
Row and Column Select
Output Buffer
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Results

3.1 Detector Array
The schematic for the pixel was tested using a transient analysis and a pulsed current source as the photocurrent input.  The duty cycle of the current source was approximately 90%, which is similar to what would be expected in an actual interferometer.  The frequency was set at 2kHz, a typical refresh rate for higher order adaptive optical systems.  The two bias voltages were implemented using a ramped voltage to find optimal operation conditions.  A simulation would run with a bias voltage ramping, and upon inspection of the simulation, the ideal voltage would be determined.  These voltages were then set at the ideal value (no longer ramped).  The modulation signal was simulated with a sine-wave signal centered at 2.0V, and an amplitude of 200mV P-P.  The test schematic can be seen in Figure 3.1.1 .  Results of this simulation are presented in Figure 3.1.2 .
    The results show the capability to handle phototransistor currents lower than 150pA.  Assuming a gain of 30 in the transistor and a quantum efficiency of 30%, this corresponds to a peak flux at the detector of approximately 1x10⁸ photons per second.  The noise floor of the detector was estimated to be approximatley 10pA, so a 15:1 signal to noise ratio (or larger) should provide acceptable operation.  The refresh rate of the circuit can be in excess of 3kHz, which is much faster than nearly any existing deformable mirror controller capable of handling large numbers of actuators (more than 300).

The mapping of the Deformable mirror to the array can be seen in Figure 3.1.3 .

3.2 Row and Column Select
The operation of the Row and Column select circuit was simulated to understand the operation of the pseudo nmos implementation of the logic.  The results of this simulationare shown in Figure 3.2.1 .  These results show that the logic, although compact, does not quite swing low enough to turn of the nmos row select transistors.  To fix this, the output was twice inverted to allow full voltage swing from GND to Vdd and allow for both the row and ~row select signals to be generated.

3.3 Output Buffer

Because the ouput voltage from the pixel is merely a voltage stored in a capacitor, it is quite volatile, and needs to be buffered.  The output buffer consists of a voltage-follower arrangement.  The voltage in the sampling capacitor is always available to the gate of the nmos transistor acting as the source follower, therefore residing within the pixel cell.  The other part of the buffer resides at the periphery of the chip, with additional bias voltages supplied to assure accuracy of the replicated signal.  
    The buffer was simulated to determine accuracy.  Linearity is most important, and offsets or gain are not a concern.   The results are shown in Figure 3.3.1 .

Abstract
Introduction
Methods
Discussion
Ackowledgements

Send correspondence to: winsor@stsci.edu

07 December, 2001