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The Detector and Signal Processor
Row and Column Select
Output Buffer
System Schematic
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Methods

It is desirable to have a detector array capable of handling all of the processing of an interferogram so that image acquisition and analysis, as well as comparison with previous states is no longer necessary.  Such a device would simply output a voltage that is proportional to the signal needed to send to an actuator to correct for the distortion in the phasefront.  This would allow for nearly direct control of a deformable mirror based on the interferogram imaged onto the array.
 One method of interpreting interferograms is to employ modulation in one of the beam paths.  Modulation can create a variable delay in the phasefront of one of the beams by simply moving a flat mirror.  By looking at the direction of motion of the fringe, the necessary motion of a deformable mirror actuator to correct for the distorted wavefront can be determined.

2.1 The Detector and Signal Processor
 The amount of light incident upon the detector is expected to be quite small for many applications.  A detector with some gain is desirable to help with the signal strength under low light conditions, so a phototransistor makes a logical choice for the detector.  The size of the detector is important.  It needs to fill a large enough area of the pixel to generate an acceptable signal, yet it also needs to be small enough to undersample the fringes.  A detector that is larger than a fringe width will not be very good at detecting a fringe because the signal will not drop very much as the fringe passes across it.  For many applications, a fringe width of roughly one fourth of the inter-pixel spacing is the most extreme condition, and most conditions would experience fringe widths that are wider than this.  Therefore, a detector fill factor of ~6% to 10% was considered desirable.
 The current generated by the detector is fed into a pmos current mirror.  One copy of this current goes to the output of the chip, implemented by a row select signal triggering an nmos transistor.  The gate voltage at the current mirror is also sent to an inverting amplifier, with gate sizes three times the width of the initial transistor.  This signal is then sent to another inverting amplifier, which acts more like a comparator, generating the pulses necessary to switch an nmos transistor to sample the modulation signal.  The two inverting amplifiers have bias voltage inputs to the nmos transistors.  These bias voltages adjust the characteristics of the circuit toward a specific photocurrent.  The complete circuit is shown in Figure 2.1.1 .
 The size of the transistor for the current mirror was chosen to be 6l wide by 6l long.  This size is small enough to have low gate capacitance yet large enough to reduce the effects of manufacturing tolerances from pixel to pixel.  Having consistent performance from pixel to pixel is very important for this array, as bias voltages cannot be set for individual pixels.  The initial inverting amplifier was chosen with transistor widths three times wider than the current mirror.  This gives a boost to the current in this stage of the circuit, possibly reducing the effects of noise in this stage.  This amplifies the voltage going to the final inverting amplifier, although slowing the response time somewhat.  The final inverting amplifier creates pulses that are relatively narrow, and are sufficient to trigger the switch to sample the modulation signal.  This amplifier is purely a voltage amplifier, as the gate widths are reduced back to 6l wide by 6l long.  These transistors do not need to be any larger than this, as they act primarily as a comparator.
 The sample and hold switch is an nmos transistor, with minimal size of 4l wide x 2l long to reduce the effects of charge injection.  This switch allows the modulation signal to be sampled by a capacitor.  The capacitor is relatively large to reduce the effects of charge injection, and is implemented in layout by means of a large nmos transistor gate (the source, drain and bulk node connections of this transistor are all tied to ground).
 The voltage on the capacitor is always available to the output.  Output of the voltage occurs when a row not select signal triggers a pmos, and the capacitor voltage is output (and buffered) by means of a source follower.
    There are four input signals to each pixel, and two outputs.  The inputs consist of two bias signals that control the inverting amplifiers, the modulation signal, the row select and row not select.  The outputs are the copy of the phototransistor current and the sampled modulation voltage signal.  Input and output lines are arranged to allow for a side-buttable arrangement.  Horizontal lines are made with the metal 1 layer.  Ground, Vdd, row select and row not select are arranged to run horizontally in the cell.  The bias voltages, modulation signal, and ouput signals all run vertically on metal 2 lines.
    The full pixel schematic consists of 10 cmos transistors (5 pmos and 5 nmos) and one pnp phototransistor.  The pixel area is 116 l x 116l and the phototransistor emitter is 29l x 29l . The layout of the cell is depicted in Figure 2.1.2 .  The schematic of the pixel cell and the extracted layout were compared using Layout VS. Schematic to verify that the layout netlists match the schematic.  Since the technology files for the MOSIS AMI0.5 process do not recognize pnp devices, especially phototransistors, the schematic had to be modified to eliminate the phototransistor entirely in order for the net lists to match.  Since this is a very simple part of the circuit, and easily verified visually, this was not a concern.

2.2 Row and Column Select
    Selection of the row and column is performed by 5-bit parallel input to the chip.  The 5 bit inputs are first inverted on the chip, and wires providing the input and the inverted input are available to each decoder cell.  The decoder consists of a 5 input AND gate, and is implemented in pseudo nmos.  The output of the AND gate is twice inverted to provide a full swing from Vdd to ground, and to allow for both a row select and row not select signal available at the array.  The row and column decoder are schematically identical.  A sample decoder cell layout is shown in Figure 2.2.1 .
    The location of the row decoder was arbitrarily chosen to be on the left side of the array, and the column decoder is at the bottom of the array.  The size of the row decoder is 116 l high (must match the pixel height) by 121l wide, and is designed to be side-buttable with the pixel array.  The size of the column decoder is 128l high by 116 l wide (to match the pixel width).  The slightly larger size of the column decoder is needed for extra wires to interface with the output buffer.
    Although 5 bits allows for up to 32 different states, it was known beforehand that not all of these states would be used.  To avoid problems with scalability, there was no use of "don't care" states in the design, so the design is fully scalable for up to a 31 x 31 pixel array, with the addition of the extra decoder gates.

2.3 Output Buffer
    An output buffer is needed to preserve the integrity of the signal coming out of the chip.  To accomplish this, a source follower was implemented.  In the detector array, each pixel contains part of this buffer.  The sampled modulation signal voltage is delivered to the gate of an nmos transistor, and a row not select signal triggers a pmos transistor to connect to the other half of the output buffer residing at the periphery.  This other transistor is large enough to buffer the signal, and uses a bias voltage to set the desired linearity.
    There is one output buffer for each column, and next to each output buffer is a pass gate.  The output of the column decoder turns on the pass gate, ouputting the buffered signal.  The layout of this is depicted in Figure 2.3.1 .

2.4 Full System Schematic
    Using the tiny chip program from MOSIS, there is approximatley 3070l by 3070l of chip area to use within the padframe.  Since our pixel cells are 116 l, an array with 21 pixels on a side is possible, while still allowing enough room at the periphery for row and column decoders, an output buffer, and wires to get the signals to and from the pad frame.
    The full system schematic is shown in Figure 2.4.1 .
    The full layout, including the pad frame, is depicted in Figure 2.4.2 .
 

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07 December, 2001